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DESCRIPTION
The WM8772 is a multi-channel audio codec ideal for DVD and surround sound processing applications for home hi-fi, automotive and other audio visual equipment. A stereo 24-bit multi-bit sigma delta ADC is used. Digital audio output word lengths from 16-32 bits and sampling rates from 32kHz to 96kHz are supported. The 32-lead version allows separate ADC and DAC samples rates. Three stereo 24-bit multi-bit sigma delta DACs are used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 192kHz are supported. Each DAC channel has independent digital volume and mute control. The audio data interface supports I2S, left justified, right justified and DSP digital audio formats. The device is controlled via a 3 wire serial interface. The interface provides access to all features including channel selection, volume controls, mutes, de-emphasis and power management facilities. The device is available in a 28 lead SSOP or 32 lead TQFP.
WM8772
24-bit, 192kHz 6-Channel Codec with Volume Control
FEATURES
* Audio Performance - * * * * * 103dB SNR (`A' weighted @ 48kHz) DAC - 100dB SNR (`A' weighted @ 48kHz) ADC (TQFP) DAC Sampling Frequency: 8kHz - 192kHz ADC Sampling Frequency: 32kHz - 96kHz ADC and DAC can run at different sample rates (32 pin TQFP version only) 3-Wire SPI Serial or Hardware Control Interface Programmable Audio Data Interface Modes - * * * * I2S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths Three Independent stereo DAC outputs with independent digital volume controls Master or Slave Audio Data Interface 2.7V to 5.5V Analogue, 2.7V to 3.6V Digital supply Operation 28 lead SSOP or 32 lead TQFP Package
APPLICATIONS
* * * DVD Players Surround Sound AV Processors and Hi-Fi systems Automotive Audio
BLOCK DIAGRAM - 28 LEAD SSOP
REFADC VREFN VREFP AGND DOUT MCLK AVDD
VREFN VREFP
VMID
BCLK
DIN1
DIN2
DIN3
LRC
STEREO DAC
VREFN
LOW PASS FILTER
VOUT1L VOUT1R VOUT2L VOUT2R VOUT3L VOUT3R
AINL AINR
STEREO ADC
AUDIO INTERFACE & DIGITAL FILTERS
STEREO DAC
LOW PASS FILTER
STEREO DAC
LOW PASS FILTER
CONTROL INTERFACE
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WM8772EDS
WOLFSON MICROELECTRONICS plc
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MC/IWL
MD/DM
MUTE
ML/I2S
DVDD
DGND
MODE
Production Data, October 2005, Rev 4.2 Copyright 2005 Wolfson Microelectronics plc
WM8772 BLOCK DIAGRAM - 32 LEAD TQFP
DACVREFN DACVREFP ADCVREFN ADCMCLK* DOUT ADCLRC* ADCBCLK* DACBCLK* DACLRC* DIN1 DIN2 DIN3 DACMCLK* REFADC
Production Data
VREFN VREFP
AGND
AVDD
VMID
STEREO DAC
LOW PASS FILTER
VOUT1L VOUT1R VOUT2L VOUT2R VOUT3L VOUT3R
AINL AINR
STEREO ADC
AUDIO INTERFACE & DIGITAL FILTERS
STEREO DAC
LOW PASS FILTER
STEREO DAC
LOW PASS FILTER
CONTROL INTERFACE
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WM8772EFT
MC/IWL
MD/DM
MUTE
ML/I2S
MODE
DVDD
DGND
* extra pins on TQFP allow separate clocking of ADC and DAC
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WM8772 TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM - 28 LEAD SSOP ....................................................................1 BLOCK DIAGRAM - 32 LEAD TQFP ....................................................................2 TABLE OF CONTENTS .........................................................................................3 PIN CONFIGURATION - 28 LEAD SSOP .............................................................5 ORDERING INFORMATION ..................................................................................5 PIN CONFIGURATION 32 LEAD TQFP...............................................................6 ORDERING INFORMATION ..................................................................................6 PIN DESCRIPTION - 28 LEAD SSOP...................................................................7 PIN DESCRIPTION - 32 LEAD TQFP ...................................................................8 ABSOLUTE MAXIMUM RATINGS.........................................................................9 RECOMMENDED OPERATING CONDITIONS ...................................................10 ELECTRICAL CHARACTERISTICS ....................................................................10
TERMINOLOGY .......................................................................................................... 12
DIGITAL FILTER CHARACTERISTICS ...............................................................13
DAC FILTER RESPONSES......................................................................................... 13 ADC FILTER RESPONSES......................................................................................... 14 ADC HIGH PASS FILTER ........................................................................................... 14 DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................... 14
WM8772EDS - 28 LEAD SSOP ..........................................................................16 MASTER CLOCK TIMING....................................................................................16
DIGITAL AUDIO INTERFACE - MASTER MODE ....................................................... 16 MPU INTERFACE TIMING .......................................................................................... 19
DEVICE DESCRIPTION.......................................................................................20
INTRODUCTION ......................................................................................................... 20 AUDIO DATA SAMPLING RATES............................................................................... 20 HARDWARE CONTROL MODES ............................................................................... 21 DIGITAL AUDIO INTERFACE ..................................................................................... 23 POWERDOWN MODES ............................................................................................. 28 ZERO DETECT ........................................................................................................... 28 SOFTWARE CONTROL INTERFACE OPERATION................................................... 29
REGISTER MAP - 28 PIN SSOP ........................................................................30
CONTROL INTERFACE REGISTERS ........................................................................ 31
APPLICATIONS INFORMATION .........................................................................39
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 39 SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS ................................... 40
PACKAGE DIMENSIONS ....................................................................................42 WM8722EFT - 32 LEAD TQFP ............................................................................43 MASTER CLOCK TIMING....................................................................................43
DIGITAL AUDIO INTERFACE - MASTER MODE ....................................................... 43 MPU INTERFACE TIMING .......................................................................................... 46
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WM8772
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DEVICE DESCRIPTION.......................................................................................48
INTRODUCTION ......................................................................................................... 48 AUDIO DATA SAMPLING RATES............................................................................... 48 HARDWARE CONTROL MODES ............................................................................... 49 DIGITAL AUDIO INTERFACE ..................................................................................... 51 POWERDOWN MODES ............................................................................................. 57 ZERO DETECT ........................................................................................................... 57 SOFTWARE CONTROL INTERFACE OPERATION................................................... 57
REGISTER MAP - 32 PIN TQFP .........................................................................58
CONTROL INTERFACE REGISTERS ........................................................................ 59
APPLICATIONS INFORMATION .........................................................................69
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 69 SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS ................................... 70
PACKAGE DIMENSIONS ....................................................................................72 IMPORTANT NOTICE ..........................................................................................73
ADDRESS: .................................................................................................................. 73
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WM8772
PIN CONFIGURATION - 28 LEAD SSOP
MODE MCLK BCLK LRC DVDD DGND DIN1 DIN2 DIN3 DOUT ML/I2S MC/IWL MD/DM MUTE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
AVDD AGND VOUT3R VOUT3L VOUT2R VOUT2L VOUT1R VOUT1L AINL AINR VMID VREFP VREFN REFADC
ORDERING INFORMATION
DEVICE WM8772SEDS/V TEMPERATURE RANGE -25 to +85oC
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PACKAGE 28-lead SSOP (Pb free) 28-lead SSOP (Pb free, tape and reel)
MOISTURE SENSITIVITY LEVEL MSL3 MSL3
PEAK SOLDERING TEMPERATURE 260oC 260oC
WM8772SEDS/RV Note: Reel quantity = 2,000
-25 to +85 C
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WM8772 PIN CONFIGURATION 32 LEAD TQFP
VOUT3L VOUT2R VOUT1R VOUT2L VOUT1L AINR AINL VMID
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24 23 22 25 26 27 28 29 30 31 32 1 ADCLRC 2 DACLRC 3 DVDD VOUT3R AGND AVDD MODE ADCMCLK DACMLCK ADCBCLK DACBCLK
21
20 19
18 17 16 15 14 13 12 11 10 9 DACVREFP DACVREFN ADCVREFN REFADC MUTE MD/DM MC/IWL ML/I2S
4 DGND
5 DIN1
6 DIN2
7 DIN3
8 DOUT
ORDERING INFORMATION
DEVICE WM8772SEFT/V WM8772SEFT/RV TEMPERATURE RANGE -25 to +85oC -25 to +85 C
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PACKAGE 32-lead TQFP (Pb free) 32-lead TQFP (Pb free, tape and reel)
MOISTURE SENSITIVITY LEVEL MSL2 MSL2
PEAK SOLDERING TEMPERATURE 260oC 260 C
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Note: Reel quantity = 2,200
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WM8772
PIN DESCRIPTION - 28 LEAD SSOP
PIN 1 NAME MODE TYPE Digital input Control format selection 0 = Software control 1 = Hardware control Master clock; 256, 384, 512 or 768fs (fs = word clock frequency) (combined ADCMCLK and DACMCLK) Audio interface bit clock (combined ADCBCLK and DACBCLK) Audio left/right word clock (combined ADCLRC and DACLRC) Digital positive supply Digital negative supply DAC channel 1 data input DAC channel 2 data input DAC channel 3 data input ADC data output Software Mode: Serial interface Latch signal Hardware Mode: Input Audio Data Format Software Mode: Serial control interface clock Hardware Mode: Audio data input word length Software Mode: Serial interface data Hardware Mode: De-emphasis selection DAC Zero Flag output or DAC mute input ADC reference buffer decoupling pin; 10uF external decoupling ADC and DAC negative supply DAC positive reference supply Midrail divider decoupling pin; 10uF external decoupling ADC right input ADC left input DAC channel 1 left output DAC channel 1 right output DAC channel 2 left output DAC channel 2 right output DAC channel 3 left output DAC channel 3 right output Analogue negative supply and substrate connection Analogue positive supply DESCRIPTION
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MCLK BCLK LRC DVDD DGND DIN1 DIN2 DIN3 DOUT ML/I2S MC/IWL MD/DM MUTE REFADC VREFN VREFP VMID AINR AINL VOUT1L VOUT1R VOUT2L VOUT2R VOUT3L VOUT3R AGND AVDD
Digital input Digital input/output Digital input/output Supply Supply Digital input Digital input Digital input Digital output Digital input Digital input Digital input Digital input/output Analogue output Supply Supply Analogue output Analogue input Analogue input Analogue output Analogue output Analogue output Analogue output Analogue output Analogue output Supply Supply
Note: Digital input pins have Schmitt trigger input buffers.
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WM8772 PIN DESCRIPTION - 32 LEAD TQFP
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME ADCLRC DACLRC DVDD DGND DIN1 DIN2 DIN3 DOUT ML/I2S MC/IWL MD/DM MUTE REFADC ADCVREFN DACVREFN DACVREFP VMID AINR AINL VOUT1L VOUT1R VOUT2L VOUT2R VOUT3L VOUT3R AGND AVDD MODE TYPE Digital Input/Output Digital Input/Output Supply Supply Digital Input Digital Input Digital Input Digital Output Digital Input Digital Input Digital Input Digital Input/Output Analogue Output Supply Supply Supply Analogue Output Analogue Input Analogue Input Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Supply Supply Digital Input ADC left/right word clock DAC left/right word clock Digital positive supply Digital negative supply DAC channel 1 data input DAC channel 2 data input DAC channel 3 data input ADC data output Software Mode: Serial interface Latch signal Hardware Mode: Input Audio Data Format Software Mode: Serial control interface clock Hardware Mode: Audio data input word length Software Mode: Serial interface data Hardware Mode: De-emphasis selection DAC Zero Flag output or DAC Mute Input DESCRIPTION
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ADC reference buffer decoupling pin; 10uF external decoupling ADC negative supply DAC negative supply DAC positive reference supply Midrail divider decoupling pin; 10uF external decoupling ADC right input ADC left input DAC channel 1 left output DAC channel 1 right output DAC channel 2 left output DAC channel 2 right output DAC channel 3 left output DAC channel 3 right output Analogue negative supply and substrate connection Analogue positive supply Control format selection 0 = Software control 1 = Hardware control Master ADC clock; 256, 384, 512 or 768fs (fs = word clock frequency) Master DAC clock; 256, 384, 512 or 768fs (fs = word clock frequency) ADC audio interface bit clock DAC audio interface bit clock
29 30 31 32
ADCMCLK DACMCLK ADCBCLK DACBCLK
Digital Input Digital Input Digital Input/Output Digital Input/Output
Note: Digital input pins have Schmitt trigger input buffers.
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WM8772
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs 1 Voltage range analogue inputs 1 Master Clock Frequency Operating temperature range, TA Storage temperature after soldering Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) Notes: 1. Analogue and digital grounds must always be within 0.3V of each other. -25C -65C MIN -0.3V -0.3V DGND -0.3V AGND -0.3V MAX +5V +7V DVDD +0.3V AVDD +0.3V 37MHz +85C +150C Refer to Ordering Information, p5 and p6 +183C
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WM8772 RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Ground Difference DGND to AGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD. SYMBOL DVDD AVDD, VREFP AGND, VREFN, DGND -0.3 TEST CONDITIONS MIN 2.7 2.7 0 0 +0.3 TYP MAX 3.6 5.5
Production Data
UNIT V V V V
ELECTRICAL CHARACTERISTICS
Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, 32-pin TQFP version unless otherwise stated. ADC/DAC in Slave Mode unless otherwise stated. PARAMETER 0dBFs Full scale output voltage SNR (Note 1,2,4) SNR (Note 1,2,4) SNR (Note 1,2,4) SNR (Note 1,2,4) A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted @ fs = 192kHz A-weighted @ fs = 48kHz, AVDD = 3.3V A-weighted @ fs = 96kHz, AVDD = 3.3V DNR A-weighted, -60dB full scale input 1kHz, 0dB.Fs 1kHz Input, 0dB gain PSRR 1kHz 100mVp-p 20Hz to 20kHz 100mVp-p 90 95 SYMBOL TEST CONDITIONS MIN TYP 1.0 x VREFP/5 103 102 101 99 MAX UNIT Vrms dB dB dB dB DAC Performance (Load = 10k, 50pF)
SNR (Note 1,2,4)
99
dB
Dynamic Range (Note 2,4) Total Harmonic Distortion (THD) Mute Attenuation DAC channel separation Power Supply Rejection Ratio
103 -90 100 100 50 45 -80
dB dB dB dB dB dB
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WM8772
Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, 32-pin TQFP version unless otherwise stated. ADC/DAC in Slave Mode unless otherwise stated. PARAMETER ADC Performance Input Signal Level (0dB) Input resistance Input capacitance SNR (Note 1,2,4) SNR (Note 1,2,4) A-weighted, 0dB gain @ fs = 48kHz A-weighted, 0dB gain @ fs = 96kHz 64 x OSR A-weighted, 0dB gain @ fs = 48kHz, AVDD = 3.3V A-weighted, 0dB gain @ fs = 96kHz, AVDD = 3.3V 64 x OSR kHz, 0dBFs 1kHz, -1dBFs ADC Channel Separation Mute Attenuation Power Supply Rejection Ratio PSRR 1kHz Input 1kHz Input, 0dB gain 1kHz 100mVpp 20Hz to 20kHz 100mVpp Digital Logic Levels (CMOS Levels) Input LOW level Input HIGH level Input leakage current Input capacitance Output LOW Output HIGH Analogue Reference Levels Reference voltage Potential divider resistance Supply Current Analogue supply current Digital supply current Notes: 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). AVDD, VREFP = 5V DVDD = 3.3V 45 16 mA mA VVMID RVMID VREFP to VMID and VMID to VREFN VREFP/2 - 50mV VREFP/2 50 VREFP/2 + 50mV V k VOL VOH IOL=1mA IOH= -1mA 0.9 x DVDD VIL VIH 0.7 x DVDD 0.2 5 0.1 x DVDD 1 0.3 x DVDD V V A pF V V 80 2.0 x REFADC/5 20 10 100 100 Vrms k pF dB dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
SNR (Note 1,2,4)
93
dB
SNR (Note 1,2,4)
93
dB
Total Harmonic Distortion (THD)
-80 -82 90 90 50 45
dB dB dB dB dB dB
3.
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WM8772 TERMINOLOGY
1. 2.
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Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
3. 4. 5. 6.
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WM8772
DIGITAL FILTER CHARACTERISTICS
PARAMETER Passband Passband ripple Stopband Stopband Attenuation Passband Passband ripple Stopband Stopband Attenuation Table 1 Digital Filter Characteristics f > 0.555fs 0.555fs -60 dB f > 0.5465fs DAC Filter 0.05 dB -3dB 0.487fs 0.05 dB 0.444fs 0.5465fs -65 dB TEST CONDITIONS ADC Filter 0.01 dB -6dB 0 0.5fs 0.01 dB 0.4535fs MIN TYP MAX UNIT
DAC FILTER RESPONSES
0.2 0 0.15 -20 0.1
Response (dB)
Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100
-0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
-120
Figure 1 DAC Digital Filter Frequency Response - 44.1, 48 and 96KHz
Figure 2 DAC Digital Filter Ripple -44.1, 48 and 96kHz
0.2 0 0 -20
Response (dB)
Response (dB)
-0.2
-40
-0.4
-60
-0.6
-0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 3 DAC Digital Filter Frequency Response - 192KHz
Figure 4 DAC Digital Filter Ripple - 192kHz
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WM8772 ADC FILTER RESPONSES
0.02 0 0.015 0.01 -20
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Response (dB)
-40
Response (dB)
0.005 0 -0.005 -0.01 -0.015 -0.02
-60
-80
0
0.5
1
1.5 Frequency (Fs)
2
2.5
3
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (Fs)
0.35
0.4
0.45
0.5
Figure 5 ADC Digital Filter Frequency Response
Figure 6 ADC Digital Filter Ripple
ADC HIGH PASS FILTER
The WM8772EDS has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial.
H ( z) =
1 - z -1 1 - 0.9995z -1
DIGITAL DE-EMPHASIS CHARACTERISTICS
0 1 0.5 -2 0
Response (dB)
-4
Response (dB)
-0.5 -1 -1.5 -2
-6
-8 -2.5 -10 0 2 4 6 8 10 Frequency (kHz) 12 14 16 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16
Figure 7 De-Emphasis Frequency Response (32kHz)
Figure 8 De-Emphasis Error (32KHz)
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0 0.4 0.3 -2 0.2
Response (dB)
Response (dB)
WM8772
-4
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20
Figure 9 De-Emphasis Frequency Response (44.1KHz)
0
Figure 10 De-Emphasis Error (44.1KHz)
1 0.8
-2
0.6 0.4
Response (dB)
-4
Response (dB)
0.2 0 -0.2 -0.4
-6
-8
-0.6 -0.8
-10 0 5 10 15 Frequency (kHz) 20
-1 0 5 10 15 Frequency (kHz) 20
Figure 11 De-Emphasis Frequency Response (48kHz)
Figure 12 De-Emphasis Error (48kHz)
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WM8772EDS - 28 LEAD SSOP PAGES 12 TO 36 DESCRIBE THE OPERATION OF THE WM8772EDS 28 LEAD SSOP PRODUCT VARIANT. PAGES 37 TO 66 DESCRIBE THE OPERATION OF THE WM8772EFT 32 LEAD TQFP PRODUCT VARIANT.
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WM8772EDS - 28 LEAD SSOP
MASTER CLOCK TIMING
t MCLKL MCLK tMCLKH t MCLKY
Figure 13 ADC and DAC Master Clock Timing Requirements Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time MCLK Duty cycle Table 2 Master Clock Timing Requirements tMCLKH tMCLKL tMCLKY 11 11 28 40:60 60:40 ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL AUDIO INTERFACE - MASTER MODE
BCLK LRC DSP/ ENCODER/ DECODER DOUT DIN1/2/3
3
WM8772 CODEC
Figure 14 Audio Interface - Master Mode
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WM8772EDS - 28 LEAD SSOP
BCLK (Output) tDL LRC (Output) tDDA DOUT
DIN1/2/3 tDST
Figure 15 Digital Audio Data Timing - Master Mode Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER LRC propagation delay from BCLK falling edge DOUT propagation delay from BCLK falling edge DIN1/2/3 setup time to BCLK rising edge DIN1/2/3 hold time from BCLK rising edge SYMBOL tDL tDDA tDST tDHT TEST CONDITIONS MIN 0 0 10 10 TYP MAX 10 10 UNIT ns ns ns ns
tDHT
Audio Data Input Timing Information
Table 3 Digital Audio Data Timing - Master Mode
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WM8772EDS - 28 LEAD SSOP
DIGITAL AUDIO INTERFACE - SLAVE MODE
Production Data
LRC WM8772 CODEC BCLK DOUT DIN1/2/3
3
DSP ENCODER/ DECODER
Figure 16 Audio Interface - Slave Mode
tBCH BCLK tBCY LRC
tBCL
tDS DIN1/2/3 tDD DOUT
tLRH
tLRSU
tDH
Figure 17 Digital Audio Data Timing - Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low LRC set-up time to BCLK rising edge LRC hold time from BCLK rising edge DIN1/2/3 set-up time to BCLK rising edge DIN1/2/3 hold time from BCLK rising edge SYMBOL tBCY tBCH tBCL tLRSU tLRH tDS tDH TEST CONDITIONS MIN 50 20 20 10 10 10 10 TYP MAX UNIT ns ns ns ns ns ns ns
Audio Data Input Timing Information
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WM8772EDS - 28 LEAD SSOP
Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER DOUT propagation delay from BCLK falling edge SYMBOL tDD TEST CONDITIONS MIN 0 TYP MAX 10 UNIT ns
Table 4 Digital Audio Data Timing - Slave Mode
MPU INTERFACE TIMING
tCSL ML/I2S tSCY tSCH MC/IWL tSCL tSCS tCSS
tCSH
MD/DM tDSU tDHO
LSB
Figure 18 SPI Compatible Control Interface Input Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated PARAMETER MC/IWL rising edge to ML/I2S rising edge MC/IWL pulse cycle time MC/IWL pulse width low MC/IWL pulse width high MD/DM to MC/IWL set-up time MC/IWL to MD/DM hold time ML/I2S pulse width low ML/I2S pulse width high ML/I2S rising to MC/IWL rising SYMBOL tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS MIN 60 80 30 30 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns
Table 5 3-Wire SPI Compatible Control Interface Input Timing Information
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WM8772EDS - 28 LEAD SSOP DEVICE DESCRIPTION
INTRODUCTION
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WM8772EDS is a complete 6-channel DAC, 2-channel ADC audio codec, including digital interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multibit sigma delta DACs with digital volume controls on each channel and output smoothing filters. The device is implemented as three separate stereo DACs and a stereo ADC in a single package and controlled by a single interface. Each stereo DAC has its own data input DIN1/2/3, the stereo ADC has it's own data output DOUT. The word clock LRC, bit clock BCLK and master clock MCLK are shared between them. The Audio Interface may be configured to operate in either master or slave mode. In Slave mode LRC and BCLK are all inputs. In Master mode LRC and BCLK are all outputs. Each DAC has its own digital volume control that is adjustable in 0.5dB steps. The digital volume controls may be operated independently. In addition, a zero cross detect circuit is provided for each DAC for the digital volume controls. The digital volume control detects a transition through the zero point before updating the volume. This minimises audible clicks and `zipper' noise as the gain values change. Control of internal functionality of the device is by 3-wire serial or pin programmable control interface. The software control interface may be asynchronous to the audio data interface as control data will be re-synchronised to the audio processing internally. Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided for the DAC, for operation of both the ADC and DAC master clocks of 256fs, 384fs, 512fs and 768fs is provided. In Slave mode selection between clock rates is automatically controlled. In master mode, the sample rate is set by control bits RATE. Audio sample rates (fs) from less than 8ks/s up to 192ks/s are allowed for the DAC and from less than 32ks/s up to 96ks/s for the ADC, provided the appropriate master clock is input. The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP serial port interface.
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master system clock can be applied directly through the MCLK input pin with no software configuration necessary. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC and DAC. The master clock for WM8772EDS supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz (for DAC operation only). For ADC operation sample rates from 256fs to 768fs are supported. The master clock is used to operate the digital filters and the noise shaping circuits. In Slave mode the WM8772EDS has a master clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 master clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The master clocks must be synchronised with LRC, although the WM8772EDS is tolerant of phase variations or jitter on this clock. Table 6 shows the typical master clock frequency inputs for the WM8772EDS. The signal processing for the WM8772EDS typically operates at an oversampling rate of 128fs for both ADC and DAC. The exception to this for the DAC is for operation with a 128/192fs system clock, e.g. for 192kHz operation, when the oversampling rate is 64fs. For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs.
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SAMPLING RATE (LRC) 32kHz 44.1kHz 48kHz 96kHz 192kHz System Clock Frequency (MHz) 128fs 4.096 5.6448 6.144 12.288 24.576 192fs 6.144 8.467 9.216 18.432 36.864 256fs 8.192 11.2896 12.288 24.576 384fs 12.288 16.9340 18.432 36.864 512fs 16.384 22.5792 24.576 768fs 24.576 33.8688 36.864
Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable
Table 6 System Clock Frequencies Versus Sampling Rate (ADC does not support 128fs and 192fs)
HARDWARE CONTROL MODES
When the MODE pin is held high, the following hardware modes of operation are available. Note: When in hardware mode the ADC and DAC will only run in slave mode. MUTE AND AUTOMUTE OPERATION In both hardware and software modes, MUTE controls the selection of MUTE directly, and can be used to enable and disable the automute function. This pin becomes an output when left floating and indicates infinite ZERO detect (IZD) has been detected. DESCRIPTION 0 1 Floating Normal Operation Mute DAC channels Enable IZD, MUTE becomes an output to indicate when IZD occurs. L=IZD detected, H=IZD not detected.
Table 7 Mute and Automute Control Figure 19 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024 or more input samples the outputs will be connected directly to VMID if IZD is set. When MUTE is deasserted, the output will restart immediately from the current input sample.
1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006
Figure 19 Application and Release of Soft Mute
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The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. The automute function detects a series of ZERO value audio samples of 1024 samples long being applied to both channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR'ed through a 10k resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert mute. If MUTE is tied low, AUTOMUTED is overridden and will not mute unless the IZD register bit is set. If MUTE is driven from a bi-directional source, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) and can be used to drive external mute circuits. AUTOMUTED will be removed as soon as any channel receives a non-ZERO input. A diagram showing how the various Mute modes interact is shown below Figure 20.
IZD (Register Bit) AUTOMUTED (Internal Signal) 10k MUTE PIN SOFTMUTE (Internal Signal)
MUTE (Register Bit)
Figure 20 Selection Logic for MUTE Modes
INPUT FORMAT SELECTION
In hardware mode, ML/I2S and MC/IWL become input controls for selection of input data format type and input data word length for both the ADC and DAC. ML/I2S 0 0 1 1 Table 8 Input Format Selection Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that the left/right clocks (LRC) are high for a minimum of 24 bit clocks (BCLK) and low for a minimum of 24 bit clocks. MC/IWL 0 1 0 1 INPUT DATA MODE 24-bit right justified 20-bit right justified 16-bit I2S 24-bit I2S
DE-EMPHASIS CONTROL
In hardware mode, the MD/DM pin becomes an input control for selection of de-emphasis filtering to be applied. MD/DM 0 1 Table 9 De-emphasis Control DE-EMPHASIS Off On
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DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In both Master and Slave modes DIN1/2/3 are always inputs to the WM8772EDS and DOUT is always an output. The default is Slave mode. In Slave mode, LRC and BCLK are inputs to the WM8772EDS (Figure 21). DIN1/2/3 and LRC are sampled by the WM8772EDS on the rising edge of BCLK. ADC data is output on DOUT and changes on the falling edge of BCLK. By setting the control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3 and LRC are sampled on the falling edge of BCLK and DOUT changes on the rising edge of BCLK.
LRC WM8772 CODEC BCLK DOUT DIN1/2/3
3
DSP ENCODER/ DECODER
Figure 21 Slave Mode In Master mode, LRC and BCLK are outputs from the WM8772EDS (Figure 22). LRC and BCLK are generated by the WM8772EDS. DIN1/2/3 are sampled by the WM8772EDS on the rising edge of BCLK so the controller must output DAC data that changes on the falling edge of BCLK. ADC data is output on DOUT and changes on the falling edge of BCLK. By setting control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3 are sampled on the falling edge of BCLK, and DOUT changes on the rising edge of BCLK.
BCLK WM8772 CODEC LRC DOUT DIN1/2/3
3
DSP/ ENCODER/ DECODER
Figure 22 Master Mode
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AUDIO INTERFACE FORMATS
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Audio data is applied to the internal DAC filters, or output from the ADC filters, via the Digital Audio Interface. 5 popular interface formats are supported: * * * * * Left Justified mode Right Justified mode I2S mode DSP mode A DSP mode B
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. In left justified, right justified and I2S modes, the digital audio interface receives DAC data on the DIN1/2/3 inputs and outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with LRC indicating whether the left or right channel is present. LRC is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes, the minimum number of BCLKs per LRC period is 2 times the selected word length. LRC must be high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on LRC is acceptable provided the above requirements are met. In DSP mode A or Mode B, all 6 DAC channels are time multiplexed onto DIN1. LRC is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRC period is 6 times the selected word length. Any mark to space ratio is acceptable on LRC provided the rising edge is correctly positioned. The ADC data may also be output in DSP mode A or mode B, with LRC used as a frame sync to identify the MSB of the first word. The minimum number of BCLKs per LRC period is 2 times the selected word length if only the ADC is being operated.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8772EDS on the first rising edge of BCLK following a LRC transition. The MSB of the ADC data is output on DOUT and changes on the same falling edge of BCLK as LRC and may be sampled on the rising edge of BCLK. LRC is high during the left samples and low during the right samples (Figure 23).
1/fs
LEFT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK
RIGHT CHANNEL
DIN1/2/3/ DOUT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 23 Left Justified Mode Timing Diagram
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RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8772EDS on the rising edge of BCLK preceding a LRC transition. The LSB of the ADC data is output on DOUT and changes on the falling edge of BCLK preceding a LRC transition and may be sampled on the rising edge of BCLK. LRC are high during the left samples and low during the right samples (Figure 24).
1/fs
LEFT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK
RIGHT CHANNEL
DIN1/2/3/ DOUT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 24 Right Justified Mode Timing Diagram
I S MODE
In I2S mode, the MSB of DIN1/2/3 is sampled by the WM8772EDS on the second rising edge of BCLK following a LRC transition. The MSB of the ADC data is output on DOUT and changes on the first falling edge of BCLK following an LRC transition and may be sampled on the rising edge of BCLK. LRC are low during the left samples and high during the right samples.
2
1/fs
LEFT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK
1 BCLK 1 BCLK
3 n-2 n-1 n 1 2 3
RIGHT CHANNEL
DIN1/2/3/ DOUT
1
2
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 25 I2S Mode Timing Diagram
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DSP MODE A
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In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8772EDS on the second rising edge on BCLK following a LRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 26).
Figure 26 DSP Mode Audio Interface - Mode A Slave, DAC
1 BCLK 1/fs 1 BCLK
DACLRC
DACBCLK CHANNEL 1 LEFT DIN1
1 2 n-1 n 1 2
CHANNEL 1 RIGHT
n-1 n
CHANNEL 2 LEFT
1 2
CHANNEL 3 RIGHT
n-1 n
NO VALID DATA
MSB
LSB
Input Word Length (IWL)
Figure 27 DSP Mode Audio Interface - Mode A Master, DAC The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of BCLK following a low to high LRC transition and may be sampled on the rising edge of BCLK. The right channel ADC data is contiguous with the left channel data (Figure 26)
Figure 28 DSP Mode Audio Interface - Mode A Slave, ADC
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1 BCLK
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1 BCLK 1/fs
ADCLRC
ADCBCLK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n-1
n
1
2
n-1
n
MSB
LSB
Input Word Length (IWL)
Figure 29 DSP Mode Audio Interface - Mode A Master, ADC
DSP MODE B
In DSP mode B, the MSB of DAC channel 1 left data is sampled by the WM8772EDS on the first BCLK rising edge following a LRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 30).
Figure 30 DSP Mode Audio Interface - Mode B Slave, DAC
1/fs
DACLRC
DACBCLK CHANNEL 1 LEFT DIN1
1 2 n-1 n 1 2
CHANNEL 1 RIGHT
n-1 n
CHANNEL 2 LEFT
1 2
CHANNEL 3 RIGHT
n-1 n
NO VALID DATA
1
MSB
LSB
Input Word Length (IWL)
Figure 31 DSP Mode Audio Interface - Mode B Master, DAC The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of BCLK as the low to high LRC transition and may be sampled on the rising edge of BCLK. The right channel ADC data is contiguous with the left channel data (Figure 32).
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Figure 32 DSP Mode Audio Interface - Mode B Slave, ADC
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n-1
n
1
2
n-1
n
1
MSB
LSB
Input Word Length (IWL)
Figure 33 DSP Mode Audio Interface - Mode B Master, ADC In both DSP mode A and mode B, DACL1 is always sent first, followed immediately by DACR1 and the data words for the other 6 channels. No BCLK edges are allowed between the data words. The word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right.
POWERDOWN MODES
The WM8772EDS has powerdown control bits allowing specific parts of the WM8772EDS to be powered off when not being used. Control bit ADCPD powers off the ADC. The three stereo DACs each have a separate powerdown control bit, DACPD[2:0] allowing individual stereo DACs to be powered off when not in use. Setting ADCPD and DACPD[2:0] will powerdown everything except the references VMID and REFADC. These may be powered down by setting PDWN. Setting PDWN will override all other powerdown control bits. It is recommended that the ADC and DACs are powered down before setting PDWN.
ZERO DETECT
The WM8772EDS has a zero detect circuit for each DAC channel that detects when 1024 consecutive zero samples have been input. The MUTE pin output may be programmed to output the zero detect signal (see Table 10) which may then be used to control external muting circuits. A `1' on MUTE indicates a zero detect. The zero detect may also be used to automatically enable DAC mute by setting IZD. DZFM[1:0] 00 01 10 11 MUTE All channels zero Channel 1 zero Channel 2 zero Channel 3 zero
Table 10 Zero Flag Output Select
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SOFTWARE CONTROL INTERFACE OPERATION
The WM8772EDS is controlled using a 3-wire serial interface in software mode or pin programmable in hardware mode. The control mode is selected by the state of the MODE pin.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is used to latch the program data. MD/DM is sampled on the rising edge of MC/IWL. The 3-wire interface protocol is shown in Figure 34.
ML/I2S
MC/IWL
MD/DM
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 34 3-Wire SPI Compatible Interface 1. 2. 3. B[15:9] are Control Address Bits B[8:0] are Control Data Bits ML/I2S is edge sensitive - the data is latched on the rising edge of ML/I2S.
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The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8772EDS can be configured using the Control Interface. All unused bits should be set to `0'.
REGISTER R0(00h) R1(01h) B15 0 0 B14 0 0 B13 0 0 B12 0 0 B11 0 0 B10 0 0 B9 0 1 B8 UPDATE UPDATE PL[8:5] R2(02h) 0 0 0 0 0 1 0 IZD ATC All DAC PHASE[8:6] UPDATE UPDATE UPDATE UPDATE UPDATE DEEMP[8:6] RATE[8:6] ADC OSR 0 0 010 MS IWL[5:4] BCP LDA2[7:0] RDA2[7:0] LDA3[7:0] RDA3[7:0] MASTDA[7:0] DMUTE[5:3] PWRDNALL 0 DZFM[2:1] DACPD[3:1] 00 AMUTE ALL 00
ZCD ADCPD
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT 011111111 011111111
LDA1[7:0] RDA1[7:0] PDWN DEEMP All DAC FMT[1:0] MUTE
100100000
R3(03h) R4(04h) R5(05h) R6(06h) R7(07h) R8(08h) R9(09h) R10(0Ah) R11(0Bh)
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1 1
0 1 1 1 1 0 0 0 0
1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1
LRP
000000000 011111111 011111111 011111111 011111111 011111111 000000000 010000000 001000000
R12(0Ch)
0
0
0
1
1
0
0
MPD
0
0 RESET
ADCHP
AMUTEL AMUTER
000000000 000000000
R31(1Fh)
0
0
1
1
1
1
1
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CONTROL INTERFACE REGISTERS
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS 0000010 DAC Channel Control BIT 3 LABEL ATC DEFAULT 0 DESCRIPTION Attenuator Control Mode: 0: Right channels use right attenuations 1: Right channels use left attenuations
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function: REGISTER ADDRESS 0000010 DAC Channel Control BIT 4 LABEL IZD DEFAULT 0 DESCRIPTION Infinite Zero Mute Enable 0 : Disable inifinite zero mute 1: Enable infinite zero mute
With IZD enabled, applying 1024 consecutive zero input samples each stereo channel will cause that stereo channel outputs to be muted to VMID. Mute will be removed as soon as that stereo channel receives a non-zero input.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: REGISTER ADDRESS 0000010 DAC Control BIT 8:5 LABEL PL[3:0] DEFAULT 1001 PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DESCRIPTION Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2
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ADC AND DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits: REGISTER ADDRESS 0000011 Interface Control BIT 1:0 LABEL FMT [1:0] DEFAULT 00
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DESCRIPTION Interface Format Select: 00 : Right justified mode 01: Left justified mode 10: I2S mode 11: DSP mode A or B
In left justified, right justified or I S modes, the LRP register bit controls the polarity of LRC. If this bit is set high, the expected polarity of LRC will be the opposite of that shown Figure 23, Figure 24 and Figure 25. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the LRP register bit is used to select between mode A and mode B. REGISTER ADDRESS 0000011 Interface Control BIT 2 LABEL LRP DEFAULT 0 DESCRIPTION In left/right/I2S Modes: LRC Polarity (normal) 0 : Normal LRC polarity 1: Inverted LRC polarity In DSP Mode: 0 : DSP mode A 1: DSP mode B By default, LRC and DIN1/2/3 are sampled on the rising edge of BCLK and should ideally change on the falling edge. By default, LRC and DOUT are sampled on the rising edge of BCLK and should ideally change on the falling edge. Data sources that change LRC and DOUT on the rising edge of BCLK can be supported by setting the BCP register bit. Data sources that change LRC and DIN1/2/3 on the rising edge of BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in Figure 23 to Figure 33. REGISTER ADDRESS 0000011 Interface Control BIT 3 LABEL BCP DEFAULT 0 DESCRIPTION BCLK Polarity (DSP Modes): 0: Normal BCLK polarity 1: Inverted BCLK polarity
2
The IWL[1:0] bits are used to control the input word length. REGISTER ADDRESS 0000011 Interface Control BIT 5:4 LABEL IWL [1:0] DEFAULT 00 DESCRIPTION Input Word Length: 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data
Note: 32-bit right justified mode is not supported. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8772EDS pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that LRC is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. A number of options are available to control how data from the Digital Audio Interface is applied to the DAC channels.
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DAC OUTPUT PHASE
The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted REGISTER ADDRESS 0000011 DAC Phase BIT 8:6 LABEL PHASE [2:0] DEFAULT 000 Bit 0 1 2 DESCRIPTION DAC DAC1L/R DAC2L/R DAC3L/R Phase 1 = invert 1 = invert 1 = invert
DIGITAL ZERO CROSS-DETECT
The Digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit DZCEN. REGISTER ADDRESS 0001001 DAC Control BIT 0 LABEL ZCD DEFAULT 0 DESCRIPTION DAC Digital Volume Zero Cross Disable: 0: Zero cross detect enabled 1: Zero cross detect disabled
MUTE FLAG OUTPUT
The DZFM control bits allow the selection of the six DAC channel zero flag bits for output on the MUTEB pin. A `1' on MUTE indicates 1024 consecutive zero input samples to the DAC channels selected. REGISTER ADDRESS 0001001 Zero Flag BIT 2:1 LABEL DZFM[1:0] DEFAULT 00 DESCRIPTION Selects the output MUTE pin (A `1' indicates 1024 consecutive zero input samples on the DAC channels selected. 00: All channels zero 01: Channel 1 zero 10: Channel 2 zero 11: Channel 3 zero
DAC MUTE MODES
The WM8772EDS has individual mutes for each of the three DAC channels. Setting MUTE for a channel will apply a `soft' mute to the input of the digital filters of the channel muted. REGISTER ADDRESS 0001001 DAC Mute BIT 5:3 LABEL DMUTE [2:0] DEFAULT 000 DESCRIPTION DAC Soft Mute Select
DMUTE [2:0] 000 001 010 011 100 101 110
DAC CHANNEL 1 Not MUTE MUTE Not MUTE MUTE Not MUTE MUTE Not MUTE
DAC CHANNEL 2 Not MUTE Not MUTE MUTE MUTE Not MUTE Not MUTE MUTE
DAC CHANNEL 3 Not MUTE Not MUTE Not MUTE Not MUTE MUTE MUTE MUTE
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REGISTER ADDRESS 0000010 DAC Mute BIT 0 LABEL MUTEALL DEFAULT 0
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Setting the MUTEALL register bit will apply a 'soft' mute to the input of all the DAC digital filters: DESCRIPTION Soft Mute Select: 0 : Normal operation 1: Soft mute all channels
Refer to Figure 19 for the plot of application and release of soft mute. Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the PDWN bit or setting attenuation to 0 will cause much more abrupt muting of the output.
ADC MUTE MODES
Each ADC channel also has a mute control bit, which mutes the inputs to the ADC. REGISTER ADDRESS 0001100 ADC Mute BIT 0 LABEL AMUTER DEFAULT 0 DESCRIPTION ADC Mute Select: 0 : Normal operation 1: mute ADC right ADC Mute Select: 0 : Normal operation 1: mute ADC left ADC Mute Select: 0 : Normal operation 1: mute both ADC channels
1
AMUTEL
0
2
AMUTEALL
0
DE-EMPHASIS MODE
Each stereo DAC channel has an individual de-emphasis control bit: REGISTER ADDRESS 0001001 DAC De-Emphahsis Control BIT [8:6] LABEL DEEMPH [1:0] DEFAULT 000 DESCRIPTION De-emphasis Channel Selection Select:
DEEMPH [1:0] 000 001 010 011 100 101 110
DAC CHANNEL 1 Not DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS
DAC CHANNEL 2 Not DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS
DAC CHANNEL 3 Not DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS
Refer to Figure 7, Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12 for details of the DeEmphasis performance at different sample rates.
REGISTER ADDRESS 0000010 DAC DEMP
BIT 1
LABEL DEEMP ALL
DEFAULT 0
DESCRIPTION DEMMP Select: 0 : Normal operation 1: De-emphasis all channels
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POWERDOWN MODE AND ADC/DAC DISABLE
Setting the PDWN register bit immediately powers down the DAC's on the WM8772EDS, overriding the DACD powerdown bits control bits. All trace of the previous input samples are removed, but all control register settings are preserved. When PDWN is cleared the digital filters will be reinitialised REGISTER ADDRESS 0000010 Powerdown Control BIT 2 LABEL PDWN DEFAULT 0 DESCRIPTION Power Down all DAC's Select: 0: All DAC's enabled 1: All DAC's disabled
The ADC and DACs may also be powered down individually by setting the ADCPD and DACPD disable bits. Setting ADCD will disable the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when ADCPD is unset. Each Stereo DAC channel has a separate disable DACPD[2:0]. Setting DACPD for a channel will disable the DACs and select a low power mode. REGISTER ADDRESS 0001010 Powerdown Control BIT 0 LABEL ADCPD DEFAULT 0 DESCRIPTION ADC Disable: 0: Active 1: Disable DAC Disable
3:1
DACPD[2:0]
000
DACPD [2:0] 000 001 010 011 100 101 110 111
DAC CHANNEL 1 Active DISABLE Active DISABLE Active DISABLE Active DISABLE
DAC CHANNEL 2 Active Active DISABLE DISABLE Active Active DISABLE DISABLE
DAC CHANNEL 3 Active Active Active Active DISABLE DISABLE DISABLE DISABLE
MASTER POWERDOWN
This control bit powers down the references for the whole chop. Therefore for complete powerdown, both the ADC and DACs should be powered down first before setting this bit. REGISTER ADDRESS 0001010 Interface Control BIT 4 LABEL PWRDNALL DEFAULT 0 DESCRIPTION Master Power Down Bit: 0: Not powered down 1: Powered down
MASTER MODE SELECT
Control bit MS selects between audio interface Master and Slave Modes. In Master mode LRC and BCLK are outputs and are generated by the WM8772EDS. In Slave mode LRC and BCLK are inputs to WM8772EDS. REGISTER ADDRESS 0001010 Interface Control BIT 5 LABEL MS DEFAULT 0 DESCRIPTION DAC Audio Interface Master/Slave Mode Select: 0: Slave mode 1: Master mode
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MASTER MODE LRC FREQUENCY SELECT
Production Data
In Master mode the WM8772EDS generates LRC and BCLK. These clocks are derived from the master clock and the ratio of MCLK to LRC is set by RATE. REGISTER ADDRESS 0001010 Interface Control BIT 8:6 LABEL RATE [2:0] DEFAULT 010 DESCRIPTION Master Mode MCLK:LRC Ratio Select: 000: 128fs (DAC only) 001: 192fs (DAC only) 010: 256fs 011: 384fs 100: 512fs 101: 768fs
ADC OVERSAMPLING RATE SELECT
For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. The 64fs oversampling rate is only available in modes were a 96KHz rate is supported, i.e. 256fs or 384fs. In all other modes the ADC will stay in a 128fs oversampling rate irrespective of what this bit is set to. REGISTER ADDRESS 0001011 ADC Oversampling Rate BIT LABEL 8 ADCOSR 0 ADC Oversampling Rate Select: 0: 128x oversampling 1: 64x oversampling DEFAULT DESCRIPTION
ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled using software control bit ADCHPD. REGISTER ADDRESS 0001100 ADC Control BIT 3 LABEL ADCHPD DEFAULT 0 DESCRIPTION ADC Highpass Filter Disable: 0: Highpass filter enabled 1: Highpass filter disabled
MUTE PIN DECODE
The MUTE pin can either be used an output or an input. When used as an input the MUTE pins action can controlled by setting the DZFM bit to select the corresponding DAC for applying the MUTE to. As an output its meaning is selected by the DZFM control bits. By default selecting the MUTE to represent if DAC1 has received more than 1024 midrail samples will cause the MUTE to be asserted a softmute on DAC1. Disabling the decode block will cause any logical high on the MUTE pin to apply a softmute to all DAC's. REGISTER ADDRESS 0001100 ADC Control BIT 6 LABEL MPD DEFAULT 0 DESCRIPTION MUTE Pin Decode Disable: 0: MUTE pin decode enable 1: MUTE pin decode disable
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DAC DIGITAL VOLUME CONTROL
The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers
REGISTER ADDRESS 0000000 Digital Attenuation DACL1
BIT 7:0 8
LABEL LDA1[7:0] UPDATE
DEFAULT 11111111 (0dB) Not latched
DESCRIPTION Digital Attenuation data for Left channel DACL1 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store LDA1 in intermediate latch (no change to output) 1: Store LDA1 and update attenuation on all channels Digital Attenuation data for Right channel DACR1 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA1 in intermediate latch (no change to output) 1: Store RDA1 and update attenuation on all channels. Digital Attenuation data for Left channel DACL2 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store LDA2 in intermediate latch (no change to output) 1: Store LDA2 and update attenuation on all channels. Digital Attenuation data for Right channel DACR2 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA2 in intermediate latch (no change to output) 1: Store RDA2 and update attenuation on all channels. Digital Attenuation data for Left channel DACL3 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store LDA3 in intermediate latch (no change to output) 1: Store LDA3 and update attenuation on all channels. Digital Attenuation data for Right channel DACR3 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA3 in intermediate latch (no change to output) 1: Store RDA3 and update attenuation on all channels. Digital Attenuation data for all DAC channels in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels.
0000001 Digital Attenuation DACR1
7:0 8
RDA1[6:0] UPDATE
11111111 (0dB) Not latched
0000100 Digital Attenuation DACL2
7:0 8
LDA2[7:0] UPDATE
11111111 (0dB) Not latched
0000101 Digital Attenuation DACR2
7:0 8
RDA2[7:0] UPDATE
11111111 (0dB) Not latched
0000110 Digital Attenuation DACL3
7:0 8
LDA3[7:0] UPDATE
11111111 (0dB) Not latched
0000111 Digital Attenuation DACR3
7:0 8
RDA3[7:0] UPDATE
11111111 (0dB) Not latched
0001000 Master Digital Attenuation (all channels)
7:0 8
MASTDA [7:0] UPDATE
11111111 (0dB) Not latched
L/RDAX[7:0] 00(hex) 01(hex) : : : FE(hex) FF(hex)
ATTENUATION LEVEL - dB (mute) -127dB : : : -0.5dB 0dB
Table 11 Digital Volume Control Attenuation Levels
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SOFTWARE REGISTER RESET
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Writing to register 11111 will cause a register reset, resetting all register bits to their default values. The device will be held in this reset state until a subsequent register write to any address is completed.
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 and C5 C2 to C4 C8 and C9 C6 and C10 C7 and C11 C12 R1 SUGGESTED VALUE 10F 0.1F 1F 0.1F 10F 10F 33 Filtering for VREFP. Omit if AVDD low noise. Filtering for VREP. Use 0 if AVDD low noise. DESCRIPTION De-coupling for DVDD and AVDD. De-coupling for DVDD and AVDD. Analogue input high pass filter capacitors Reference de-coupling capacitors for VMID and ADCREF pin.
Table 12 External Components Description
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SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS
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It is recommended that a lowpass filter be applied to the output from each DAC channel for Hi Fi applications. Typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta DAC structure used in WM8772EDS produces much less high frequency output noise than normal sigma delta DACs. This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment.
Figure 35 shows a suitable post DAC filter circuit, with 2x gain. Alternative inverting filter architectures might also be used with as good results.
1.0nF 10uF 1.8k 7.5k
VOUT1L
10k 680pF 4.7k 4.7k
51
OP_FIL
VOUT1R VOUT2L VOUT2R VOUT3L VOUT3R
OP_FIL OP_FIL OP_FIL OP_FIL OP_FIL
Figure 35 Recommended Post DAC Filter Circuit
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To ensure that system `pop' noise is kept to a minimum when power is applied or removed, a transistor clamp circuit arrangement may be added to the output connectors of the system. A recommended clamp circuit configuration is shown below.
Figure 36 Output Clamp Circuit When the +VS power supply is applied, PNP transistor Q10 of the trigger circuit is held on until capacitor C49 is fully charged. With transistor Q10 held `on', NPN transistors Q4 to Q9 of the clamp circuits are also switched on holding the system outputs near to GND. When capacitor C49 is fully charged transistors Q10 and Q4 to Q9 are switched off setting the outputs active. When the +VS power supply is removed, PNP transistor Q11 of the trigger circuit is switched on. In turn, transistors Q4 to Q9 of the clamp circuits are switched on holding the outputs of the evaluation board near to GND until the rest of the circuitry on the board has settled. Note: It is recommended that low Vcesat switching transistors should be used in this circuit to ensure that the clamp is applied before the rest of the circuitry has time to power down. Important: If a trigger circuit such as the one shown is to be used, it is important that the +VS supply drops quicker than any other supply to ensure that the outputs are clamped during the period when `pop' noise may occur.
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WM8772EDS - 28 LEAD SSOP PACKAGE DIMENSIONS
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)
Production Data
DM007.E
b
28
e
15
E1
E
1
D
14
GAUGE PLANE
c A A2 A1
L
0.25
L1
-C0.10 C
SEATING PLANE
Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55 0
o
Dimensions (mm) NOM --------1.75 0.30 ----10.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 JEDEC.95, MO-150
MAX 2.0 0.25 1.85 0.38 0.25 10.50 8.20 5.60 0.95 8
o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8722EFT - 32 LEAD TQFP
MASTER CLOCK TIMING
t MCLKL ADCMCLK/ DACMCLK t MCLKY
tMCLKH
Figure 37 ADC and DAC Master Clock Timing Requirements Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information ADCMCLK and DACMCLK System clock pulse width high ADCMCLK and DACMCLK System clock pulse width low ADCMCLK and DACMCLK System clock cycle time ADCMCLK and DACMCLK Duty cycle Table 13 Master Clock Timing Requirements tMCLKH tMCLKL tMCLKY 11 11 28 40:60 60:40 ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL AUDIO INTERFACE - MASTER MODE
ADCBCLK ADCLRC DACBCLK WM8772 CODEC DACLRC DOUT DIN1/2/3
3
DSP/ ENCODER/ DECODER
Figure 38 Audio Interface - Master Mode
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ADCBCLK/ DACBCLK (Outputs) ADCLRC/ DACLRC (Outputs) tDL
tDDA DOUT
DIN1/2/3 tDST
Figure 39 Digital Audio Data Timing - Master Mode Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER ADCLRC/DACLRC propagation delay from ADCBCLK/DACBCLK falling edge DOUT propagation delay from ADCBCLK falling edge DIN1/2/3 setup time to DACBCLK rising edge DIN1/2/3 hold time from DACBCLK rising edge SYMBOL tDL TEST CONDITIONS MIN 0 TYP MAX 10 UNIT ns
tDHT
Audio Data Input Timing Information
tDDA tDST tDHT
0 10 10
10
ns ns ns
Table 14 Digital Audio Data Timing - Master Mode
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DIGITAL AUDIO INTERFACE - SLAVE MODE
ADCBCLK ADCLRC WM8772 DACBCLK CODEC DACLRC DOUT DIN1/2/3
3
DSP ENCODER/ DECODER
Figure 40 Audio Interface - Slave Mode
tBCH DACBCLK/ ADCBCLK
tBCL
tBCY
DACLRC/ ADCLRC tDS DIN1/2/3 tDD DOUT tDH tLRH tLRSU
Figure 41 Digital Audio Data Timing - Slave Mode
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Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER ADCBCLK/DACBCLK cycle time ADCBCLK/DACBCLK pulse width high ADCBCLK/DACBCLK pulse width low ADCLRC/DACLRC set-up time to ADCBCLK/DACBCLK rising edge ADCLRC/DACLRC hold time from ADCBCLK/DACBCLK rising edge DIN1/2/3 set-up time to DACBCLK rising edge DIN1/2/3 hold time from DACBCLK rising edge DOUT propagation delay from ADCBCLK falling edge SYMBOL tBCY tBCH tBCL tLRSU TEST CONDITIONS MIN 50 20 20 10 TYP MAX UNIT ns ns ns ns
Audio Data Input Timing Information
tLRH
10
ns
tDS tDH tDD
10 10 0 10
ns ns ns
Table 15 Digital Audio Data Timing - Slave Mode
MPU INTERFACE TIMING
tCSL ML/I2S tSCY tSCH MC/IWL tSCL tSCS tCSS
tCSH
MD/DM tDSU tDHO
LSB
Figure 42 SPI Compatible Control Interface Input Timing
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Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated PARAMETER MC/IWL rising edge to ML/I2S rising edge MC/IWL pulse cycle time MC/IWL pulse width low MC/IWL pulse width high MD/DM to MC/IWL set-up time MC/IWL to MD/DM hold time ML/I2S pulse width low ML/I2S pulse width high ML/I2S rising to MC/IWL rising SYMBOL tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS MIN 60 80 30 30 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns
Table 16 3-Wire SPI Compatible Control Interface Input Timing Information
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WM8772EFT - 32 LEAD TQFP DEVICE DESCRIPTION
INTRODUCTION
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WM8772EFT is a complete 6-channel DAC, 2-channel ADC audio codec, including digital interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multibit sigma delta DACs with digital volume controls on each channel and output smoothing filters. The device is implemented as three separate stereo DACs and a stereo ADC in a single package and controlled by a single interface. Each stereo DAC has its own data input DIN1/2/3. DAC word clock DACLRC, DAC bit clock DACBCLK and DAC master clock DACMCLK are shared between them. The stereo ADC has it's own data output DOUT, word clock ADCLRC, bit clock ADCBCLK and ADC master clock ADCMCLK. This allows the ADC and DAC to run independently. The Audio Interface may be configured to operate in either master or slave mode. In Slave mode ADCLRC and ADCBCLK, DACLRC and DACBCLK are all inputs. In Master mode ADCLRC and ADCBCLK, DACLRC and DACBCLK are all outputs. The DAC's and ADC can be in any combination of master or slave mode. Each DAC has its own digital volume control that is adjustable in 0.5dB steps. The digital volume controls may be operated independently. In addition, a zero cross detect circuit is provided for each DAC for the digital volume controls. The digital volume control detects a transition through the zero point before updating the volume. This minimises audible clicks and `zipper' noise as the gain values change. Control of internal functionality of the device is by 3-wire serial or pin programmable control interface. The software control interface may be asynchronous to the audio data interface as control data will be re-synchronised to the audio processing internally. Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided for the DAC, and 256fs, 384fs, 512fs, and 768fs is provided for the ADC. In Slave mode selection between clock rates is automatically controlled. In master mode, the sample rate is set by control bits ADCRATE and DACRATE. Audio sample rates (fs) from less than 8ks/s up to 192ks/s are allowed for the DAC and from less than 32ks/s up to 96ks/s for the ADC, provided the appropriate master clock is input. The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP serial port interface.
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master system clock can be applied directly through the ADC and DAC MCLK input pin(s) with no software configuration necessary. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC and DAC. The DAC master clock for WM8772EFT supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (DACLRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz (for DAC operation only). The ADC master clock for WM8772EFT supports audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency (ADCLRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used to operate the digital filters and the noise shaping circuits. In Slave mode the WM8772EFT has a master clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 master clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The master clocks must be synchronised with ADCLRC and DACLRC respectively, although the WM8772EFT is tolerant of phase variations or jitter on this clock. Table 6 shows the typical master clock frequency inputs for the WM8772EFT.
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The signal processing for the WM8772EFT typically operates at an oversampling rate of 128fs for both ADC and DAC. The exception to this for the DAC is for operation with a 128/192fs system clock, e.g. for 192kHz operation, when the oversampling rate is 64fs. For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. SAMPLING RATE (DACLRC/ ADCLRC) 32kHz 44.1kHz 48kHz 96kHz 192kHz System Clock Frequency (MHz) 128fs 4.096 5.6448 6.144 12.288 24.576 192fs 6.144 8.467 9.216 18.432 36.864 256fs 8.192 11.2896 12.288 24.576 384fs 12.288 16.9340 18.432 36.864 512fs 16.384 22.5792 24.576 768fs 24.576 33.8688 36.864
Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable
Table 17 System Clock Frequencies Versus Sampling Rate (ADC does not support 128fs and 192fs)
HARDWARE CONTROL MODES
When the MODE pin is held high, the following hardware modes of operation are available. Note: When in hardware mode the ADC and DAC will only run in slave mode.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes, MUTE controls the selection of MUTE directly, and can be used to enable and disable the automute function. This pin becomes an output when left floating and indicates infinite ZERO detect (IZD) has been detected. DESCRIPTION 0 1 Floating Normal Operation Mute DAC channels Enable IZD, MUTE becomes an output to indicate when IZD occurs. L=IZD detected, H=IZD not detected.
Table 18 Mute and Automute Control Figure 43 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024 or more input samples the outputs will be connected directly to VMID if IZD is set. When MUTE is deasserted, the output will restart immediately from the current input sample.
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1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006
Figure 43 Application and Release of Soft Mute The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. The automute function detects a series of ZERO value audio samples of 1024 samples long being applied to both channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR'ed through a 10k resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert mute. If MUTE is tied low, AUTOMUTED is overridden and will not mute unless the IZD register bit is set. If MUTE is driven from a bi-directional source, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) and can be used to drive external mute circuits. AUTOMUTED will be removed as soon as any channel receives a non-ZERO input. A diagram showing how the various Mute modes interact is shown below Figure 20.
IZD (Register Bit) AUTOMUTED (Internal Signal) 10k MUTE PIN SOFTMUTE (Internal Signal)
MUTE (Register Bit)
Figure 44 Selection Logic for MUTE Modes
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INPUT FORMAT SELECTION
In hardware mode, ML/I2S and MC/IWL become input controls for selection of input data format type and input data word length for both the ADC and DAC. ML/I2S 0 0 1 1 Table 19 Input Format Selection Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that the left/right clocks (ADCLRC and DACLRC) are high for a minimum of 24 bit clocks (ADCBCLK and DACBCLK) and low for a minimum of 24 bit clocks. MC/IWL 0 1 0 1 INPUT DATA MODE 24-bit right justified 20-bit right justified 16-bit I2S 24-bit I2S
DE-EMPHASIS CONTROL
In hardware mode, the MD/DM pin becomes an input control for selection of de-emphasis filtering to be applied. MD/DM 0 1 Table 20 De-emphasis Control DE-EMPHASIS Off On
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
The audio interface operates in either Slave or Master mode, selectable using the DACMS and ADCMS control bits. In both Master and Slave modes DIN1/2/3 are always inputs to the WM8772EFT and DOUT is always an output. The default is Slave mode for ADC and DAC. In Slave mode, ADCLRC, DACLRC and ADCBCLK, DACBCLK are inputs to the WM8772EFT (Figure 21). DIN1/2/3, ADCLRC and DACLRC are sampled by the WM8772EFT on the rising edge of ADCBCLK and DACBCLK respectively. ADC data is output on DOUT and changes on the falling edge of ADCBCLK. By setting the control bit DACBCP the polarity of DACBCLK may be reversed so that DIN1/2/3 and DACLRC are sampled on the falling edge of DACBCLK. By setting the control bit ADCBCP the polarity of ADCBCLK may be reversed so that ADCLRC is sampled on the falling edge of ADCBCLK and DOUT changes on the rising edge of ADCBCLK.
ADCBCLK ADCLRC WM8772 DACBCLK CODEC DACLRC DOUT DIN1/2/3
3
DSP ENCODER/ DECODER
Figure 45 Slave Mode In Master mode, ADCLRC, DACLRC, ADCBCLK and DACBCLK are outputs from the WM8772EFT (Figure 22). ADCLRC, DACLRC, ADCBCLK and DACBCLK are generated by the WM8772EFT.
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DIN1/2/3 are sampled by the WM8772EFT on the rising edge of DACBCLK so the controller must output DAC data that changes on the falling edge of DACBCLK. ADC data is output on DOUT and changes on the falling edge of ADCBCLK. By setting control bit DACBCP the polarity of DACBCLK may be reversed so that DIN1/2/3 are sampled on the falling edge of DACBCLK. By setting control bit ADCBCP the polarity of ADCBCLK may be reversed so that DOUT changes on the rising edge of ADCBCLK.
ADCBCLK ADCLRC DACBCLK WM8772 CODEC DACLRC DOUT DIN1/2/3
3
DSP/ ENCODER/ DECODER
Figure 46 Master Mode
AUDIO INTERFACE FORMATS
Audio data is applied to the internal DAC filters, or output from the ADC filters, via the Digital Audio Interface. 5 popular interface formats are supported: * * * * * Left Justified mode Right Justified mode I2S mode DSP mode A DSP mode B
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. In left justified, right justified and I2S modes, the digital audio interface receives DAC data on the DIN1/2/3 inputs and outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with ADCLRC or DACLRC indicating whether the left or right channel is present. ADCLRC or DACLRC is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes, the minimum number of DACBCLK/ADCBCLK's per DACLRC/ADCLRC period is 2 times the selected word length. ADCLRC/DACLRC must be high for a minimum of word length DACBCLK/ADCBCLK's and low for a minimum of word length DACBCLK/ADCBCLK's. Any mark to space ratio on ADCLRC/DACLRC is acceptable provided the above requirements are met. In DSP mode A or mode B, all 6 DAC channels are time multiplexed onto DIN1. DACLRC is used as a frame sync signal to identify the MSB of the first word. The minimum number of DACBCLK's per DACLRC period is 6 times the selected word length. Any mark to space ratio is acceptable on DACLRC provided the rising edge is correctly positioned. The ADC data may also be output in DSP mode A or mode B, with ADCLRC used as a frame sync to identify the MSB of the first word. The minimum number of ADCBCLK's per ADCLRC period is 2 times the selected word length
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LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8772EFT on the first rising edge of DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples (Figure 47).
1/fs
LEFT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK
RIGHT CHANNEL
DIN1/2/3/ DOUT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 47 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8772EFT on the rising edge of DACBCLK preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples ( Figure 48).
1/fs
LEFT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK
RIGHT CHANNEL
DIN1/2/3/ DOUT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 48 Right Justified Mode Timing Diagram
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I S MODE
2
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In I2S mode, the MSB of DIN1/2/3 is sampled by the WM8772EFT on the second rising edge of BCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK
1 BCLK 1 BCLK
3 n-2 n-1 n 1 2 3
RIGHT CHANNEL
DIN1/2/3/ DOUT
1
2
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 49 I2S Mode Timing Diagram
DSP MODE A
In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8772EFT on the second rising edge on DACBCLK following a DACLRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 50).
Figure 50 DSP Mode Audio Interface - Mode A Slave, DAC
1 BCLK 1/fs 1 BCLK
DACLRC
DACBCLK CHANNEL 1 LEFT DIN1
1 2 n-1 n 1 2
CHANNEL 1 RIGHT
n-1 n
CHANNEL 2 LEFT
1 2
CHANNEL 3 RIGHT
n-1 n
NO VALID DATA
MSB
LSB
Input Word Length (IWL)
Figure 51 DSP Mode Audio Interface - Mode A Master, DAC
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The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of ADCBCLK following a low to high ADCLRC transition and may be sampled on the rising edge of ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 52)
Figure 52 DSP Mode Audio Interface - Mode A Slave, ADC
1 BCLK 1/fs
1 BCLK
ADCLRC
ADCBCLK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n-1
n
1
2
n-1
n
MSB
LSB
Input Word Length (IWL)
Figure 53 DSP Mode Audio Interface - Mode A Master, ADC
DSP MODE B
In DSP mode B, the MSB of DAC channel 1 left data is sampled by the WM8772EFT on the first DACBCLK rising edge following a DACLRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 54).
Figure 54 DSP Mode Audio Interface - Mode B Slave, DAC
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1/fs
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DACLRC
DACBCLK CHANNEL 1 LEFT DIN1
1 2 n-1 n 1 2
CHANNEL 1 RIGHT
n-1 n
CHANNEL 2 LEFT
1 2
CHANNEL 3 RIGHT
n-1 n
NO VALID DATA
1
MSB
LSB
Input Word Length (IWL)
Figure 55 DSP Mode Audio Interface - Mode B Master, DAC The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of ADCBCLK as the low to high ADCLRC transition and may be sampled on the rising edge of ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 56).
Figure 56 DSP Mode Audio Interface - Mode A Slave, ADC
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n-1
n
1
2
n-1
n
1
MSB
LSB
Input Word Length (IWL)
Figure 57 DSP Mode Audio Interface - Mode B Master, ADC In both DSP mode A and mode B , DACL1 is always sent first, followed immediately by DACR1 and the data words for the other 6 channels. No BCLK edges are allowed between the data words. The word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right.
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POWERDOWN MODES
The WM8772EFT has powerdown control bits allowing specific parts of the WM8772EFT to be powered off when not being used. Control bit ADCPD powers off the ADC. The three stereo DACs each have a separate powerdown control bit, DACPD[2:0] allowing individual stereo DACs to be powered off when not in use. Setting ADCPD and DACPD[2:0] will powerdown everything except the references VMID and REFADC. These may be powered down by setting PDWN. Setting PDWN will override all other powerdown control bits. It is recommended that the ADC and DACs are powered down before setting PDWN.
ZERO DETECT
The WM8772EFT has a zero detect circuit for each DAC channel that detects when 1024 consecutive zero samples have been input. The MUTE pin output may be programmed to output the zero detect signal (see Table 10) which may then be used to control external muting circuits. A `1' on MUTE indicates a zero detect. The zero detect may also be used to automatically enable DAC mute by setting IZD. DZFM[1:0] 00 01 10 11 MUTE All channels zero Channel 1 zero Channel 2 zero Channel 3 zero
Table 21 Zero Flag Output Select
SOFTWARE CONTROL INTERFACE OPERATION
The WM8772EFT is controlled using a 3-wire serial interface in software mode or pin programmable in hardware mode. The control mode is selected by the state of the MODE pin. The control interfaces are 5V tolerant; meaning that the control interface input signals ML/I2S, MC/IWL and MD/DM may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by DVDD. MUTE and MODE are also 5V tolerant.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is used to latch the program data. MD/DM is sampled on the rising edge of MC/IWL. The 3-wire interface protocol is shown in Figure 34.
ML/I2S
MC/IWL
MD/DM
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 58 3-Wire SPI Compatible Interface 4. 5. 6. B[15:9] are Control Address Bits B[8:0] are Control Data Bits ML/I2S is edge-sensitive - the data is latched on the rising edge of ML/I2S.
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Production Data
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8772EFT can be configured using the Control Interface. All unused bits should be set to `0'.
REGISTER R0(00h) R1(01h) B15 0 0 B14 0 0 B13 0 0 B12 0 0 B11 0 0 B10 0 0 B9 0 1 B8 UPDATE UPDATE PL[8:5] R2(02h) 0 0 0 0 0 1 0 IZD ATC All DAC PHASE[8:6] UPDATE UPDATE UPDATE UPDATE UPDATE DEEMP[8:6] DACIWL[5:4] DACBCP DACLRP B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 011111111 011111111 PDWN DEEMP All DAC DACFMT[1:0] 000000000 011111111 011111111 011111111 011111111 011111111 DZFM[2:1] ZCD 000000000 MUTE 100100000
LDA1[7:0] RDA1[7:0]
R3(03h) R4(04h) R5(05h) R6(06h) R7(07h) R8(08h) R9(09h)
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 1 1
0 1 1 1 1 0 0
1 0 0 1 1 0 0
1 0 1 0 1 0 1
LDA2[7:0] RDA2[7:0] LDA3[7:0] RDA3[7:0] MASTDA[7:0] DMUTE[5:3] PWRDN ALL ADCMS
R10(0Ah)
0
0
0
1
0
1
0 ADC OSR 0
DACRATE[8:6]
DACMS
DACPD[3:1]
ADCPD
010000000
R11(0Bh)
0
0
0
1
0
1
1
ADCRATE[7:5]
ADCIWL[3:2] AMUTE ALL
ADCFMT[1:0]
001000000
R12(0Ch)
0
0
0
1
1
0
0
SYNC
MPD
ADCBCP
ADCLRP RESET
ADCHP
AMUTEL AMUTER
000000000 000000000
R31(1Fh)
0
0
1
1
1
1
1
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CONTROL INTERFACE REGISTERS
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS 0000010 DAC Channel Control BIT 3 LABEL ATC DEFAULT 0 DESCRIPTION Attenuator Control Mode: 0: Right channels use right attenuations 1: Right channels use left attenuations
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function: REGISTER ADDRESS 0000010 DAC Channel Control BIT 4 LABEL IZD DEFAULT 0 DESCRIPTION Infinite zero mute enable 0: Disable infinite zero mute 1: Enable infinite zero mute
With IZD enabled, applying 1024 consecutive zero input samples to each input will cause the relevant DAC to be muted to VMID. Mute will be removed as soon as that channel receives a non-zero input.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: REGISTER ADDRESS 0000010 DAC Control BIT 8:5 LABEL PL[3:0] DEFAULT 1001 PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DESCRIPTION Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2
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DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the DACFMT[1:0] register bits: REGISTER ADDRESS 0000011 Interface Control BIT 1:0 LABEL DACFMT [1:0] DEFAULT 00
Production Data
DESCRIPTION Interface Format Select: 00 : Right justified mode 01: Left justified mode 10: I2S mode 11: DSP mode A or B
In left justified, right justified or I S modes, the DACLRP register bit controls the polarity of DACLRC. If this bit is set high, the expected polarity of DACLRC will be the opposite of that shown Figure 23, Figure 24 and Figure 25. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the DACLRP register bit is used to select between mode A and mode B. REGISTER ADDRESS 0000011 Interface Control BIT 2 LABEL DACLRP DEFAULT 0 DESCRIPTION In Left/Right/I2S Modes: DACLRC Polarity (normal) 0 : Normal DACLRC polarity 1: Inverted DACLRC polarity In DSP Mode: 0 : DSP mode A 1: DSP mode B By default, DACLRC and DIN1/2/3 are sampled on the rising edge of DACBCLK and should ideally change on the falling edge. Data sources that change DACLRC and DIN1/2/3 on the rising edge of DACBCLK can be supported by setting the BCP register bit. Setting DACBCP to 1 inverts the polarity of DACBCLK to the inverse of that shown in Figure 47 to Figure 57. REGISTER ADDRESS 0000011 Interface Control BIT 3 LABEL DACBCP DEFAULT 0 DESCRIPTION DACBCLK Polarity (DSP Modes) 0 : Normal BCLK polarity 1: Inverted BCLK polarity
2
The DACIWL[1:0] bits are used to control the input word length. REGISTER ADDRESS 0000011 Interface Control BIT 5:4 LABEL DACIWL [1:0] DEFAULT 00 DESCRIPTION Input Word Length: 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data
Note: If 32-bit mode is selected in right justified mode, the WM8772EFT defaults to 24 bits. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8772EFT pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that DACLRC is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. A number of options are available to control how data from the Digital Audio Interface is applied to the DAC channels.
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DAC OUTPUT PHASE
The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted REGISTER ADDRESS 0000011 DAC Phase BIT 8:6 LABEL PHASE [2:0] DEFAULT 000 Bit 0 1 2 DESCRIPTION DAC DAC1L/R DAC2L/R DAC3L/R Phase 1 = invert 1 = invert 1 = invert
DIGITAL ZERO CROSS-DETECT
The Digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit DZCEN. REGISTER ADDRESS 0001001 DAC Control BIT 0 LABEL ZCD DEFAULT 0 DESCRIPTION DAC Digital Volume Zero Cross Disable: 0: Zero cross detect enabled 1: Zero cross detect disabled
MUTE FLAG OUTPUT
The DZFM control bits allow the selection of the six DAC channel zero flag bits for output on the MUTEB pin. A `1' on MUTE indicates 1024 consecutive zero input samples to the DAC channels selected. REGISTER ADDRESS 0001001 Zero Flag BIT 2:1 LABEL DZFM[1:0] DEFAULT 00 DESCRIPTION Selects the output MUTE pin (A `1' indicates 1024 consecutive zero input samples on the DAC channels selected. 00: All channels zero 01: Channel 1 zero 10: Channel 2 zero 11: Channel 3 zero
DAC MUTE MODES
The WM8772EFT has individual mutes for each of the three DAC channels. Setting MUTE for a channel will apply a `soft' mute to the input of the digital filters of the channel muted. REGISTER ADDRESS 0001001 DAC Mute BIT 5:3 LABEL DMUTE [2:0] DEFAULT 000 DESCRIPTION DAC Soft Mute Select
DMUTE [2:0] 000 001 010 011 100 101 110
DAC CHANNEL 1 Not MUTE MUTE Not MUTE MUTE Not MUTE MUTE Not MUTE
DAC CHANNEL 2 Not MUTE Not MUTE MUTE MUTE Not MUTE Not MUTE MUTE
DAC CHANNEL 3 Not MUTE Not MUTE Not MUTE Not MUTE MUTE MUTE MUTE
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REGISTER ADDRESS 0000010 DAC Mute BIT 0 LABEL MUTEALL DEFAULT 0
Production Data
Setting the MUTEALL register bit will apply a 'soft' mute to the input of all the DAC digital filters: DESCRIPTION Soft Mute Select: 0 : Normal operation 1: Soft mute all channels
Refer to Figure 43 for the plot of application and release of soft mute. Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the PDWN bit or setting attenuation to 0 will cause much more abrupt muting of the output.
ADC MUTE MODES
Each ADC channel also has a mute control bit, which mutes the inputs to the ADC. REGISTER ADDRESS 0001100 ADC Mute BIT 0 LABEL AMUTER DEFAULT 0 DESCRIPTION ADC Mute Select: 0 : Normal operation 1: mute ADC right ADC Mute Select: 0 : Normal operation 1: mute ADC left ADC Mute Select: 0 : Normal operation 1: mute both ADC channels
1
AMUTEL
0
2
AMUTEALL
0
DE-EMPHASIS MODE
Each stereo DAC channel has an individual de-emphasis control bit: REGISTER ADDRESS 0001001 DAC De-emphahsis Control BIT [8:6] LABEL DEEMPH [1:0] DEFAULT 000 DESCRIPTION De-emphasis Channel Selection Select:
DEEMPH [1:0] 000 001 010 011 100 101 110
DAC CHANNEL 1 Not DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS
DAC CHANNEL 2 Not DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS
DAC CHANNEL 3 Not DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS
Refer to Figure 7, Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12 for details of the DeEmphasis performance at different sample rates. REGISTER ADDRESS 0000010 DAC DEMP BIT 1 LABEL DEEMP ALL DEFAULT 0 DESCRIPTION DEMMP Select: 0 : Normal operation 1: De-emphasis all channels
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POWERDOWN MODE AND ADC/DAC DISABLE
Setting the PDWN register bit immediately powers down the DAC's on the WM8772EFT, overriding the DACD powerdown bits control bits. All trace of the previous input samples are removed, but all control register settings are preserved. When PDWN is cleared the digital filters will be reinitialised REGISTER ADDRESS 0000010 Powerdown Control BIT 2 LABEL PDWN DEFAULT 0 DESCRIPTION Power Down all DAC's Select: 0: All DAC's enabled 1: All DAC's disabled
The ADC and DACs may also be powered down individually by setting the ADCPD and DACPD disable bits. Setting ADCD will disable the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when ADCPD is unset. Each Stereo DAC channel has a separate disable DACPD[2:0]. Setting DACPD for a channel will disable the DACs and select a low power mode. Resetting DACD will reinitialise the digital filters. REGISTER ADDRESS 0001010 Powerdown Control BIT 0 LABEL ADCPD DEFAULT 0 DESCRIPTION ADC Disable: 0: Active 1: Disable DAC Disable
3:1
DACPD [2:0]
000
DACPD [2:0] 000 001 010 011 100 101 110 111
DAC CHANNEL 1 Active DISABLE Active DISABLE Active DISABLE Active DISABLE
DAC CHANNEL 2 Active Active DISABLE DISABLE Active Active DISABLE DISABLE
DAC CHANNEL 3 Active Active Active Active DISABLE DISABLE DISABLE DISABLE
MASTER POWERDOWN
This control bit powers down the references for the whole chop. Therefore for complete powerdown, both the ADC and DACs should be powered down first before setting this bit. REGISTER ADDRESS 0001010 Interface Control BIT 4 LABEL PWRDNALL DEFAULT 0 DESCRIPTION Master Power Down Bit: 0: Not powered down 1: Powered down
DAC MASTER MODE SELECT
Control bit DACMS selects between audio interface Master and Slave Modes. In Master mode DACLRC and DACBCLK are outputs and are generated by the WM8772EFT. In Slave mode DACCLRC, DACLRC and DACBCLK are inputs to WM8772EFT. REGISTER ADDRESS 0001010 Interface Control BIT 5 LABEL DACMS DEFAULT 0 DESCRIPTION DAC Audio Interface Master/Slave Mode Select: 0: Slave Mode 1: Master Mode
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MASTER MODE DACLRC FREQUENCY SELECT
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In Master mode the WM8772EFT generates DACLRC and DACBCLK. These clocks are derived from the master clock and the ratio of DACMCLK to DACLRC is set by DACRATE. REGISTER ADDRESS 0001010 Interface Control BIT 8:6 LABEL DACRATE [2:0] DEFAULT 010 DESCRIPTION Master Mode DACMCLK:DACLRC Ratio Select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs 101: 768fs
ADC DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the ADCFMT[1:0] register bits: REGISTER ADDRESS 0001011 Interface Control BIT 1:0 LABEL ADCFMT[1:0] DEFAULT 00 DESCRIPTION Interface Format Select 00: Right justified mode 01: Left justified mode 10: I2S mode 11: DSP mode A or B
The ADCIWL[1:0] bits are used to control the input word length. REGISTER ADDRESS 0001011 Interface Control BIT 3:2 LABEL ADCIWL[1:0] DEFAULT 00 DESCRIPTION Input Word Length 00: 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data
Note: 32-bit right justified mode is not supported. In all modes, the data is signed 2's complement.
ADC MASTER MODE SELECT
Control bit ADCMS selects between audio interface Master and Slave Modes. In Master mode ADCLRC and ADCBCLK are outputs and are generated by the WM8772EFT. In Slave mode ADCLRC and ADCBCLK are inputs to WM8772EFT. REGISTER ADDRESS 0001011 Interface Control BIT 4 LABEL ADCMS DEFAULT 0 DESCRIPTION ADC Audio Interface Master/Slave Mode Select: 0: Slave mode 1: Master mode
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MASTER MODE ADCLRC FREQUENCY SELECT
In Master mode the WM8772EFT generates ADCLRC and ADCBCLK. These clocks are derived from the master clock and the ratio of ADCMCLK to ADCLRC is set by ADCRATE. REGISTER ADDRESS 0001011 ADCLRC and ADCBCLK Frequency Select BIT 7:5 LABEL ADCRATE [2:0] DEFAULT 010 DESCRIPTION Master Mode ADCMCLK:ADCLRC Ratio Select: 010: 256fs 011: 384fs 100: 512fs 101: 768fs
ADC OVERSAMPLING RATE SELECT
For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. The 64fs oversampling rate is only available in modes were a 96KHz rate is supported, i.e. 256fs or 384fs. In all other modes the ADC will stay in a 128fs oversampling rate irrespective of what this bit is set to. REGISTER ADDRESS 0001011 ADC Oversampling Rate BIT 8 LABEL ADCOSR DEFAULT 0 DESCRIPTION ADC Oversampling Rate Select 0: 128x oversampling 1: 64x oversampling
ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled using software control bit ADCHPD. REGISTER ADDRESS 0001100 ADC Control BIT 3 LABEL ADCHPD DEFAULT 0 DESCRIPTION ADC Highpass Filter Disable: 0: Highpass filter enabled 1: Highpass filter disabled
In left justified, right justified or I2S modes, the ADCLRP register bit controls the polarity of ADCLRC. If this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown in Figure 47, Figure 48, and Figure 49. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the ADCLRP register bit is used to select between modes A and B. REGISTER ADDRESS 0001100 Interface Control BIT 4 LABEL ADCLRP DEFAULT 0 DESCRIPTION In Left/Right/I2S Modes: ADCLRC Polarity (normal) 0: normal DACLRC polarity 1: inverted DACLRC polarity In DSP Mode: 0: DSP mode A 1: DSP mode B By default, DACLRC and DOUT are sampled on the rising edge of ADCBCLK and should ideally change on the falling edge. Data sources that change ADCLRC and DOUT on the rising edge of ADCBCLK can be supported by setting the ADCBCP register bit. Setting ADCBCP to 1 inverts the polarity of ADCBCLK to the inverse of that shown in Figure 47 to Figure 57.
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REGISTER ADDRESS 0001100 Interface Control
BIT 5
LABEL ADCBCP
DEFAULT 0
DESCRIPTION ADCBCLK Polarity (DSP Modes): 0: normal BCLK polarity 1: inverted BCLK polarity
MUTE PIN DECODE
The MUTE pin can either be used an output or an input. When used as an input the MUTE pins action can controlled by setting the DZFM bit to select the corresponding DAC for applying the MUTE to. As an output its meaning is selected by the DZFM control bits. By default selecting the MUTE to represent if DAC1 has received more than 1024 midrail samples will cause the MUTE to be asserted a softmute on DAC1. Disabling the decode block will cause any logical high on the MUTE pin to apply a softmute to all DACs. REGISTER ADDRESS 0001100 ADC Control BIT 6 LABEL MPD DEFAULT 0 DESCRIPTION MUTE Pin Decode Disable: 0: MUTE pin decode enable 1: MUTE pin decode disable
DAC TO ADC SYNC
If the DAC and ADC use the same MCLK, and they are operating in the same fs mode setting the SYNC bit will improve performance by synchronising the internal clock between the two blocks. Setting this at any other time may or may not improve or degrade the performance of the device. REGISTER ADDRESS 0001100 SYNC Control BIT 7 LABEL SYNC DEFAULT 0 DESCRIPTION SYNC Function: 0: Disable 1: Enable
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DAC DIGITAL VOLUME CONTROL
The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers
REGISTER ADDRESS 0000000 Digital Attenuation DACL1
BIT 7:0 8
LABEL LDA1[7:0] UPDATE
DEFAULT 11111111 (0dB) Not latched
DESCRIPTION Digital Attenuation data for Left channel DACL1 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store LDA1 in intermediate latch (no change to output) 1: Store LDA1 and update attenuation on all channels Digital Attenuation data for Right channel DACR1 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA1 in intermediate latch (no change to output) 1: Store RDA1 and update attenuation on all channels. Digital Attenuation data for Left channel DACL2 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store LDA2 in intermediate latch (no change to output) 1: Store LDA2 and update attenuation on all channels. Digital Attenuation data for Right channel DACR2 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA2 in intermediate latch (no change to output) 1: Store RDA2 and update attenuation on all channels. Digital Attenuation data for Left channel DACL3 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store LDA3 in intermediate latch (no change to output) 1: Store LDA3 and update attenuation on all channels. Digital Attenuation data for Right channel DACR3 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA3 in intermediate latch (no change to output) 1: Store RDA3 and update attenuation on all channels. Digital Attenuation data for all DAC channels in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels.
0000001 Digital Attenuation DACR1
7:0 8
RDA1[6:0] UPDATE
11111111 (0dB) Not latched
0000100 Digital Attenuation DACL2
7:0 8
LDA2[7:0] UPDATE
11111111 (0dB) Not latched
0000101 Digital Attenuation DACR2
7:0 8
RDA2[7:0] UPDATE
11111111 (0dB) Not latched
0000110 Digital Attenuation DACL3
7:0 8
LDA3[7:0] UPDATE
11111111 (0dB) Not latched
0000111 Digital Attenuation DACR3
7:0 8
RDA3[7:0] UPDATE
11111111 (0dB) Not latched
0001000 Master Digital Attenuation (all channels)
7:0 8
MASTDA [7:0] UPDATE
11111111 (0dB) Not latched
L/RDAX[7:0] 00(hex) 01(hex) : : : FE(hex) FF(hex)
ATTENUATION LEVEL - dB (mute) -127dB : : : -0.5dB 0dB
Table 22 Digital Volume Control Attenuation Levels
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SOFTWARE REGISTER RESET
Production Data
Writing to register 11111 will cause a register reset, resetting all register bits to their default values. The device will be held in this reset state until a subsequent register write to any address is completed.
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 and C5 C2 to C4 C8 and C9 C6 and C10 C7 and C11 C12 R1 SUGGESTED VALUE 10F 0.1F 1F 0.1F 10F 10F 33 Filtering for VREFP. Omit if AVDD low noise. Filtering for VREP. Use 0 if AVDD low noise. DESCRIPTION De-coupling for DVDD and AVDD. De-coupling for DVDD and AVDD. Analogue input high pass filter capacitors Reference de-coupling capacitors for VMID and ADCREF pin.
Table 23 External Components Description
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Production Data
It is recommended that a lowpass filter be applied to the output from each DAC channel for Hi Fi applications. Typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta DAC structure used in WM8772EFT produces much less high frequency output noise than normal sigma delta DACs. This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment. Figure 59 shows a suitable post DAC filter circuit, with 2x gain. Alternative inverting filter architectures might also be used with as good results.
1.0nF 10uF 1.8k 7.5k
VOUT1L
10k 680pF 4.7k 4.7k
51
OP_FIL
VOUT1R VOUT2L VOUT2R VOUT3L VOUT3R
OP_FIL OP_FIL OP_FIL OP_FIL OP_FIL
Figure 59 Recommended Post DAC Filter Circuit
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To ensure that system `pop' noise is kept to a minimum when power is applied or removed, a transistor clamp circuit arrangement may be added to the output connectors of the system. A recommended clamp circuit configuration is shown below.
Figure 60 Output Clamp Circuit When the +VS power supply is applied, PNP transistor Q10 of the trigger circuit is held on until capacitor C49 is fully charged. With transistor Q10 held `on', NPN transistors Q4 to Q9 of the clamp circuits are also switched on holding the system outputs near to GND. When capacitor C49 is fully charged transistors Q10 and Q4 to Q9 are switched off setting the outputs active. When the +VS power supply is removed, PNP transistor Q11 of the trigger circuit is switched on. In turn, transistors Q4 to Q9 of the clamp circuits are switched on holding the outputs of the evaluation board near to GND until the rest of the circuitry on the board has settled. Note: It is recommended that low Vcesat switching transistors should be used in this circuit to ensure that the clamp is applied before the rest of the circuitry has time to power down. Important: If a trigger circuit such as the one shown is to be used, it is important that the +VS supply drops quicker than any other supply to ensure that the outputs are clamped during the period when `pop' noise may occur.
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FT: 32 PIN TQFP (7 x 7 x 1.0 mm) DM028.A
Production Data
b
e
17
24
25
16
E1
E
32
9
1
8
c
D1 D
L A A2 A1 -Cccc C
SEATING PLANE
Symbols A A1 A2 b c D D1 E E1 e L ccc REF:
Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 0.95 1.00 1.05 0.30 0.37 0.45 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.80 BSC 0.45 0.60 0.75 o o o 0 3.5 7 Tolerances of Form and Position 0.10 JEDEC.95, MS-026
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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PD Rev 4.2 October 2005 72
Production Data
WM8772EFT - 32 LEAD TQFP
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc 26 Westfield Road Edinburgh EH11 2QB United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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PD Rev 4.2 October 2005 73

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